FIG. 1 shows a simplified illustration of an arrangement of components of a memory module. Integrated semiconductor memories HS1, HS2 and HS3, are formed, for example, as DRAM (dynamic random access memory) memories, are interconnected and connected to a memory controller MC via a bus system B. In this case, the memory controller MC and the semiconductor memories are connected to the bus system B via a data interface IMC of the memory controller and via respective data interfaces IHS1, IHS2 and IHS3 of the semiconductor memories HS1, HS2 and HS3.
In integrated semiconductor memories, a significant portion of the power loss arises in the data interface to other components. In general, a plurality of data lines are connected to the data interface of a semiconductor memory. The power loss P per data line results as P=½×U2×f×L×T, where U indicates the specified interface voltage, f indicates the clock frequency, L indicates the capacitive loading and T indicates a rate of change of data changes. In this case, the interface voltage U indicates the voltage between a data low level and a data high level. The interface voltage typically lies between 1.8 volts and 3.3 volts in present-day DRAMs. The clock frequency f corresponds to the frequency at which the semiconductor memory or the memory module is operated. The capacitive loading L arises by virtue of the fact that a data interface of a semiconductor memory is essentially loaded by capacitive loads of other semiconductor memories, or of a memory controller, which are connected to the same bus. For example, the data interface IHS1 of the semiconductor memory HS1, as illustrated in FIG. 1, is loaded by the capacitive load of terminals via which the memory controller MC and also the semiconductor memories HS2 and HS3 are connected to the bus B. The bus capacitance also likewise influences the total capacitive loading L. The rate of change T indicates the probability with which data at the data interface change from a low level to a high level or from a high level to a low level.
Particularly in the case of DRAM memories for mobile battery-operated applications, such as mobile telephones or PDAs, for example, the proportion of the total power loss made up by the interface may amount to up to 50 percent. The background is that these DRAM memories usually have 32 data lines, whereas in the PC segment DRAM memories with four or eight data lines are predominant.
The power loss is reduced at the present time by using lower voltages for DRAM memories for mobile applications as compared to corresponding DRAM memories in the PC segment. Thus, by way of example, an interface voltage of nominally 2.5 volts is specified in accordance with a JEDEC standard for DDR SDRAMs, whereas an interface voltage of nominally 1.8 volts is specified for the functionally compatible mobile variant, also referred to as LPDDR (low power double data rate) SDRAM.